1. Field of the Invention
The present invention relates to the field of electromagnetic interference (EMI) control in complementary FET switching circuits.
2. Prior Art
Electromagnetic Interference (EMI) is a common problem in modern electronic systems. Many everyday consumer products combine complex digital signal processing with radio frequency transmit and receive circuitry for communication. The former is an unintentional source of EMI that can interfere with the latter “intentional” source, as well as any other RF sources in the vicinity of the emitter. As a result, there exists stringent high frequency emissions limits on most everyday electronic equipment.
As one example, for class D amplifiers, the fast switching of the output FETs can cause strong emissions at high frequencies. For filterless class D amplifiers, the magnitude of the emissions is a strong function of the length of the wires connecting the amplifier to the speaker. Since the speaker presents an inductive load to the amplifier, the rate of change of the electric field is usually much higher than the rate of change of the magnetic field around the emitter. Therefore, the high frequency characteristics of the output switching voltage waveform mostly determine the EMI performance. There are essentially two components to this waveform: (1) the transition from negative supply to positive supply and vice versa, and (2) the ringing and settling due to various parasitic LC tank circuits around the power FETs and their packaging. To fully understand the details here, refer to FIG. 1 and note that, for an inductive load, current cannot change instantaneously in the inductor, and therefore, when both devices are OFF, current must continue to flow somewhere, and can therefore only flow through the FET parasitic diodes. Depending on the direction of the load current, the parasitic diode could either cause the output to transition to a diode drop above the positive supply rail, or a diode-drop below the negative supply rail. When one or the other of the FETs is subsequently turned ON, the load current flows through the FET, causing the output voltage to either droop toward the nearest supply rail, or to transition to the opposite supply rail.
The ringing and settling depend on the distributed LC tank circuits that include package and bond-wire inductance and parasitic FET capacitances. For example, assume for discussion that the output FET gate series resistors shown in FIG. 1 are zero. Every time the gate of one of the output FETs is switched to the supply rail, an LC tank is formed from the supply line inductance and FET gate-source and gate-drain capacitances, damped only by the ON resistance of a switch, which might only be a few ohms. The FET gate voltage can ring with a frequency of 100 s of MHz, an oscillation which will couple through to the output. This can easily be visible in the output voltage spectrum as an emissions spike at the LC tank frequency. Depending on which way the output is transitioning, and the direction of the load current, various LC tank frequencies can be observed.
The slew rate of the output transition from low to high and vice versa determines how much the wideband frequency content of the output voltage deviates from that of an ideal square waveform. For example, the frequency spectrum of a square pulse with equal and finite rise and fall times τ will exhibit harmonics that follow a sinc (sin x/x) envelope when compared to the frequency spectrum of an ideal square waveform (ideal being one with infinitely fast edges). This sinc envelope has spectral nulls at frequencies that are integer multiples of 1/τ. Making τ be 10 ns or greater under all operating conditions can therefore result in a significant emissions benefit.
Therefore it is desired that the gate voltage transitions of both FETs be controlled in such a way as to limit the output voltage slew rate, and attempt to damp the described parasitic sources of oscillation. Referring to FIG. 1, conventional means to achieve this involve either adding resistors in series with the output FET gates, or reducing the aspect ratio of the output FET gate driving switches to increase the RC time constant formed by the gate and the driving switch. Both solutions increase the transition time of the output FET gates, but the time between one FET turning OFF and the next FET turning ON is relatively poorly controlled, and will typically lead to substantial dead time (time when both switches are OFF) as shown in the typical waveforms of FIG. 2. Furthermore, for an inductive load (see FIG. 2), the point at which the output voltage transition occurs is also poorly controlled, and in fact, can occur either at the beginning or end of the dead time, depending on the direction of the load current. (Note that the direction of the load current determines which one of the parasitic FET diodes must conduct during the dead time.) This effect results in distortion. The time used for FET gate transitions leads to efficiency loss, because the FETs are operating in a high ON resistance mode for a relatively large fraction of the switching period. Finally, these shortcomings limit the maximum frequency of operation of the output power stage, and this is in itself largely contrary to high fidelity and high efficiency filterless class D circuit design art.
The foregoing discusses the prior art as related to class D amplifiers such as are frequently used to drive a speaker. However similar problems are encountered in any application that uses two or more complementary FETs as a switched output stage to drive heavy loads, including resistive, capacitive, inductive and complex loads in response to an input signal. In that regard, such circuits are considered herein, in a broad sense, as a form of class D amplifier.
Furthermore, for illustrative purposes, schematics of the prior art and disclosed invention show a single-ended speaker driver configuration. It should be noted that the invention can be readily applied to a full H-bridge load configuration, as is more common in the class D art. Considering the single-ended case merely simplifies the foregoing discussion.